remove b0 slot from AND stack frames.

src/prolog/and_stack.rs

@@ -6,7 +6,6 @@ use std::vec::Vec;
 #[derive(Clone)]
 pub struct Frame {
     pub global_index: usize,
-    pub b0: usize,
     pub e: usize,
     pub cp: CodePtr,
     perms: Vec<Addr>
@@ -16,7 +15,6 @@ impl Frame {
     fn new(global_index: usize, fr: usize, e: usize, cp: CodePtr, n: usize) -> Self {
         Frame {
             global_index,
-            b0: 0,
             e: e,
             cp: cp,
             perms: (1 .. n+1).map(|i| Addr::StackCell(fr, i)).collect()