This website requires JavaScript.
Explore
Help
Sign In
rishi
/
scryer-prolog
Watch
1
Star
0
Fork
0
You've already forked scryer-prolog
Code
Issues
Pull Requests
Actions
Packages
Projects
Releases
Wiki
Activity
Files
18a9a6434f4e52e0c6347dad3273fab6bb78d7f6
scryer-prolog
/
src
History
Mark Thom
18a9a6434f
delay attributed variables goal, naively correct dif/2
2019-04-24 20:37:31 -06:00
..
l0
fix unification bugs.
2017-01-27 21:54:53 -07:00
l1
add dumb comments
2017-02-03 00:49:16 -07:00
l2
minor tweak
2017-02-28 13:33:28 -07:00
l3
transition to l3
2017-03-04 19:22:43 -07:00
prolog
delay attributed variables goal, naively correct dif/2
2019-04-24 20:37:31 -06:00
main.rs
read from streams.
2019-04-13 18:40:17 -06:00
tests.rs
move setup_call_cleanup/3 and call_with_inference_limit/3 to non_iso
2019-04-23 08:40:10 -06:00