add use_module/{1,2} as full fledged predicates

This commit is contained in:
Mark Thom
2019-09-30 10:26:29 -06:00
parent 376b39a4ef
commit 9df14cf890
14 changed files with 261 additions and 59 deletions

View File

@@ -652,7 +652,7 @@ impl<'a, Outputter: HCValueOutputter> HCPrinter<'a, Outputter> {
});
iter.stack().pop();
self.cyclic_terms.remove(&addr);
self.cyclic_terms.swap_remove(&addr);
None
}
}