add use_module/{1,2} as full fledged predicates
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@@ -652,7 +652,7 @@ impl<'a, Outputter: HCValueOutputter> HCPrinter<'a, Outputter> {
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});
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iter.stack().pop();
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self.cyclic_terms.remove(&addr);
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self.cyclic_terms.swap_remove(&addr);
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None
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}
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}
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