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correct register threshold calculation.

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This commit is contained in:
Mark Thom
2019-03-17 21:45:30 -06:00
parent cd683c7f3d
commit 55a251d1c4
2 changed files with 7 additions and 14 deletions
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15
src/prolog/machine/attributed_variables.rs
View File

@@ -59,17 +59,10 @@ impl MachineState {
pub(super) pub(super)
fn calculate_register_threshold(&self) -> usize { fn calculate_register_threshold(&self) -> usize {
let mut count = 0; /* for all we know, all registers might be valid when we
* return from the verify_attributes interrupt. we currently
for r in 1 .. MAX_ARITY + 1 { * lack a more precise way of determining this. */
if let &Addr::HeapCell(0) = &self[RegType::Temp(r)] { MAX_ARITY
break;
}
count += 1;
}
count
} }
fn verify_attributes(&mut self) fn verify_attributes(&mut self)

6
src/prolog/machine/compile.rs
View File

@@ -341,13 +341,13 @@ fn add_module_code(wam: &mut Machine, mut module: Module, code: Code, mut indice
module.code_dir.extend(code_dir); module.code_dir.extend(code_dir);
module.op_dir.extend(op_dir.into_iter()); module.op_dir.extend(op_dir.into_iter());
for (name, arity) in indices.code_dir.keys().cloned() { for (name, arity) in indices.code_dir.keys().cloned() {
if name.owning_module() == module.module_decl.name { if name.owning_module() == module.module_decl.name {
wam.indices.dynamic_code_dir.remove(&(name.owning_module(), name, arity)); wam.indices.dynamic_code_dir.remove(&(name.owning_module(), name, arity));
} }
} }
wam.add_module(module, code); wam.add_module(module, code);
} }