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generate module-level expansion code along with rest of module code

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This commit is contained in:
Mark Thom
2019-11-24 15:47:34 -07:00
parent 7bf6a230f3
commit 4e887e3a87
2 changed files with 20 additions and 19 deletions
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17
src/prolog/machine/machine_state_impl.rs
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@@ -3080,14 +3080,15 @@ impl MachineState {
| (
HeapCellValue::Addr(v1 @ Addr::StackCell(..)),
HeapCellValue::Addr(v2 @ Addr::HeapCell(_)),
) => match (var_pairs.get(&v1).cloned(), var_pairs.get(&v2).cloned()) {
(Some(ref v2_p), Some(ref v1_p)) if *v1_p == v1 && *v2_p == v2 => continue,
(Some(_), _) | (_, Some(_)) => return true,
(None, None) => {
var_pairs.insert(v1.clone(), v2.clone());
var_pairs.insert(v2, v1);
}
},
) =>
match (var_pairs.get(&v1).cloned(), var_pairs.get(&v2).cloned()) {
(Some(ref v2_p), Some(ref v1_p)) if *v1_p == v1 && *v2_p == v2 => continue,
(Some(_), _) | (_, Some(_)) => return true,
(None, None) => {
var_pairs.insert(v1.clone(), v2.clone());
var_pairs.insert(v2, v1);
}
},
(HeapCellValue::Addr(a1), HeapCellValue::Addr(a2)) => {
if a1 != a2 {
return true;