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![Scryer Logo: Cryer](logo/scryer.png)
# Rebis Development Branch
![Art Card](logo/art_card.jpg)
This is the Rebis Development Branch (rebis-dev). This iteration of
Rebis contains sweeping changes to the instruction dispatch loop
alongside a compacted heap representation. These changes are to
enhance the performance and robustness of Scryer Prolog and to prepare
for the introduction of a mark-compacting garbage collector.
Several performance enhancing changes are due before rebis-dev will be
considered ready for merging into master, among them:
* Replacing choice points pivoting on inlined deterministic predicates
(`atom`, `var`, etc) with if/else ladders
* Inlining all built-ins and system call instructions
* Greatly reducing the number of instructions used to compile disjunctives
* Storing short atoms to heap cells without writing them to the atom table
## Phase 1
Produce an implementation of the Warren Abstract Machine in Rust, done